A field programmable gate array (FPGA) is a sheet of reconfigurable silicon that becomes whatever digital circuit you describe. This series builds real hardware on it from the ground up. It starts with the two primitives every design rests on, the lookup table and the flip-flop, and works upward through combinational logic, state machines, arithmetic, on-chip memory, pipelining, and timing closure, ending at a pipelined matrix-multiply engine of the kind that accelerates machine learning. Every module is written in synthesizable SystemVerilog, kept small enough to read in one sitting, and checked in simulation. The bias throughout is toward the way the fabric actually works rather than toward toy examples, because on an FPGA the difference between a design that meets timing and one that does not is usually a fact about the silicon.
Start hereWhat an FPGA is actually made of. The lookup table as a tiny reprogrammable truth table, the flip-flop as the only thing that remembers, and how logic slices, carry chains, block RAM, and the routing between them turn a description into a circuit.
Read the page →The primitives, and the smallest correct ways to combine them. Read in order, each page assumes the one before it.
The lookup table as a reprogrammable truth table, the flip-flop as the only element that holds state, and the logic slice, carry chain, block RAM, and digital signal processing (DSP) slice that the synthesis tools map your code onto. The map, place, and route flow explained end to end.
Multiplexers, decoders, priority encoders, comparators, and adders written in SystemVerilog, the difference between a continuous assignment and an always_comb block, and how each of them lands on the lookup tables and carry chain of the fabric.
The flip-flop in code, registers, counters, and shift registers, why a synchronous design uses one clock and a small number of resets, and the always_ff pattern with nonblocking assignment that keeps simulation and synthesis agreeing.
Moore and Mealy machines, the three-block coding style, one-hot against binary state encoding and what the fabric prefers, and a worked overlapping sequence detector.
The arithmetic and storage a real design is built around.
Adders and the carry chain, fixed-point number formats, and the hardened multiply-accumulate that makes an FPGA good at signal processing and machine-learning inference.
Distributed against block RAM, the inference templates the tools recognize, true dual-port memory, and a single-clock first-in first-out buffer built the right way.
Making it fast, and making it safe across clocks.
Trading latency for throughput, the valid bit that travels with the data, and how adding registers raises the maximum clock frequency, with a three-stage pipelined multiplier.
Setup and hold, slack, the maximum frequency equation, and the timing constraints file that tells the tools what the clocks are.
Metastability, the two-flop synchronizer for a single bit, and a Gray-code asynchronous FIFO for a bus, with testbenches that run across two clocks.
Connecting blocks together and building the accelerator.
The valid and ready handshake that connects blocks on modern FPGAs, the one rule that keeps it lossless, and a skid-buffer register slice that pipelines a stream without dropping data.
The capstone. A pipelined dot-product tile built from DSP-slice multiply-accumulates, and how a grid of them becomes the systolic array under machine-learning inference.
Self-checking testbenches, driving simulation from Python with cocotb, SystemVerilog assertions, and where formal methods prove what simulation only samples.