A design that simulates correctly still has to run at speed on real silicon, and confirming that it does is called timing closure. It is the pass where the tools add up the true delays along every path and check that each signal arrives when it must. Understanding the two constraints behind it, setup and hold, makes the timing reports readable and tells you what to change when a design does not meet its clock. This page is about those constraints and about the file that tells the tools what the clocks are in the first place.
Setup and hold
A flip-flop captures its input on the clock edge, and it needs the input to be steady for a short window around that edge. The input must be stable for a setup time $t_{su}$ before the edge and for a hold time $t_{h}$ after it. Setup is the constraint that limits speed. The signal leaves the launching flip-flop a clock-to-output delay after the edge, travels through the logic and wiring, and must arrive at the capturing flip-flop at least $t_{su}$ before the next edge. Writing $T$ for the clock period, the requirement is
$$t_{cq} + t_{logic} + t_{setup} \le T,$$
and the amount of room to spare is the slack, $T$ minus that sum. Positive slack means the path meets timing, negative slack means it fails, and the tools report the worst negative slack across the whole design as the number to fix. Hold is a different worry. It fails when a path is too short, so the new value races through and corrupts the capture of the same edge. Hold violations do not improve with a slower clock, but the tools almost always fix them automatically by padding short paths, so setup is what you spend your attention on.
Closing timing when a path fails
When the worst path has negative slack, a handful of moves recover it, in rough order of what to try first. Pipeline the path, adding a register to cut a long stretch of logic into two shorter ones, which is the most reliable fix and the reason the previous page exists. Rework the logic so the critical path is shorter, for instance by precomputing part of it a cycle earlier. Help placement keep the connected blocks close so the wiring stops eating the budget. Timing closure is mostly the discipline of reading the report, finding the worst path, understanding why it is long, and applying the cheapest of these that works.
Telling the tools about the clocks
None of this analysis can happen until the tools know what the clocks are and how fast they run, and that lives in a constraints file, written in a small Tcl-based language and carrying the extension xdc on one major vendor and sdc more broadly. The most important line defines the clock and its period, because that period is the $T$ every setup check is measured against. Other lines describe when inputs arrive and when outputs are expected relative to the clock, so paths that leave and enter the chip are analyzed too.
constraints.xdc# define a 200 MHz clock (5 ns period) on the input clock pin
create_clock -name clk -period 5.000 [get_ports clk]
# tell the tools when inputs are valid and when outputs are needed,
# relative to that clock, so the paths to the pins are checked too
set_input_delay -clock clk 1.5 [get_ports {data_in[*]}]
set_output_delay -clock clk 1.5 [get_ports {data_out[*]}]
# a slow, unrelated configuration signal that does not need timing analysis
set_false_path -to [get_ports led_status]The create_clock line is the one you cannot omit,
because without it the tools have no period to check against and will
either analyze nothing or assume a default that means nothing. The
set_false_path line is the other half of the craft,
telling the tools not to waste effort, or fail the design, on a path
that does not actually need to meet the clock, such as a status light.
Writing honest constraints is as much a part of a working design as
the logic itself, because a design that meets a clock the constraints
never described has not really been checked at all.
Everything so far has lived inside a single clock. Real systems have more than one, and moving a signal between two clocks safely is a problem with its own established answer, which is the next page.